HPC in the Cloud: China's Dark Horse Supercomputing Chip: FeiTeng

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January 19, 2012

China's Dark Horse Supercomputing Chip: FeiTeng

Michael Feldman

Chinese development of domestic microprocessors for high performance computing seems to be ramping up. The Godson-3B and ShenWei SW1600 CPUs were the first out of the gate, with the latter chip powering a Chinese petascale supercomputer. Waiting in the wings is the FeiTeng processor, an architecture that could be the one that takes Chinese supercomputing into the exascale realm.

Although, there is not a lot of information publicly available on the latest FeiTeng chip, at one time it was being promoted as "the world's first 64-bit stream processor dedicated for high-performance science computing." The architecture, which is variously known as the FeiTeng, YinHe, the YinHe FeiTeng, and the FT64, has been developed at the National University of Defense Technology (NUDT) in Hunan Province. The design work culminated in its first implementation under the FT64 moniker in 2007.

According to a paper presented at the International Symposium on Computer Architecture in 2007 (ISCA 2007) and published by the ACM that year, the FT64 architecture and instruction set was specifically designed with high performance computing in mind. The instructions are of the VLIW persuasion and nearly half of them apply to 64-bit FP operations. Not surprisingly, about 36 percent of the die is devoted to arithmetic operations.

This first-generation FeiTeng was implemented on 130nm process technology and, at 500 MHz, delivered a peak performance of 16 gigaflops. While that's nothing to get too excited about today, keep in mind that the FT64 is nearly five years old. What's more impressive is that the chip consumed a mere 8.6 watts of power, which would yield an energy efficiency of about 1.8 gigaflops/watt. The current top of the line NVIDIA GPU in the Tesla M02090, built on 2011-era 40nm technology, delivers about 2.9 gigaflops/watt.

Like its GPGPU cousin, the FT64 was meant to run as a coprocessor, driven by a host CPU. The ACM paper describes an HPC system board that had one host driving eight FT64 and communicating with each coprocessor via an on-chip host interface. Like the GPU-CPU systems of today, FT64 memory and host memory are separate.

The FT64 designers also came up with a stream programming language called SF95, which extended FORTRAN95 with 10 compiler directives to exploit the architecture. The compiler was used to benchmark the FT64 against an Itanium 2 using nine science application kernels (FFT, EP, MG, Swim, CG, Laplace, Jacobi, GEMM, and NLAG-5). Except for the CG kernel where the FT64 had just a tenth of the Itanium's performance, the stream processor was between 1 and 2.5 times faster than the Itanium on the other kernels, and 8 time faster on FFT.

However, a somewhat different picture of the architecture emerged, based on a seminar delivered last month (December 2011) at the National University of Defense Technology. The seminar abstract is provided here:

YinHe FeiTeng (YHFT) series high-performance general-purpose CPUs, aimed for high-performance computing, are developed by school of computer, National University of Defense Technology. The first generation of the YHFT CPU adapts the EPIC (Explicitly Parallel Instruction Computing) architecture. Its ISA (Instruction Set Architecture) is fully compatible with Intel Itanium2. The second generation is based on the SoC (System-on-Chip) architecture. It is composed of a general-purpose CPU and a stream processor, which is the world's first 64-bit stream processor dedicated for high-performance science computing. The processor has been successfully used in the YinHe high-performance supercomputer system as an accelerator. The research results are published at ISCA 2007 and IEEE TPDS. The third generation of the YHFT CPU is a multi-core processor. Its ISA is fully compatible with SPARC. It supports floating-point SIMD (Single Instruction Multiple Data) and multi-chip interconnection to enhance parallel processing and constitute a SMP (Symmetric Multi-Processing) system directly. The first version of this multi-core processor has been used on the TH-1A PFLOPS supercomputer systems, and the ongoing upgraded version will be taped out in the next year and used in the next generation of the TH supercomputer system.

According to this, the FT64 was actually the second generation of the architecture and was deployed in some fashion in one of the YinHe (Galaxy) supercomputers in China -- presumably this one, although theoretically there could be an even lower-profile YinHe machine in existence somewhere else.

The third generation of the FeiTeng architecture sounds more like a conventional, standalone CPU, rather than a stream accelerator per se. The reference to this latest chip being used in the TianHe-1A supercomputer, with upgraded version due to be deployed in the next generation TH machine, is especially interesting. At 4.7 peak petaflops, the NUDT's TianHe-1A is currently China's most powerful machine, but is powered by Intel Xeon and NVIDIA Tesla parts.

It's not clear how big a role the upgraded FeiTeng chips will play in the next generation TH machine, but the NUDT has not been any more loyal to chip manufacturers, than its US counterparts. In 2010, the NUDT used Intel Xeon and AMD's Radeon GPUs for its first generation petascale machine, the TianHe-1. The following year they switched to NVIDIA GPUs for the TianHe-1A.

Given China's desire to develop and use indigenous microprocessors for its HPC sector, it wouldn't be too surprising to see FeiTeng processors replace both Intel and NVIDIA parts in a future NUDT supercomputer. Obviously, supercomputing centers in the country are experimenting a lot with microprocessors, although at this point are willing to use just about anything that maximizes performance. But it's almost certain that China would want its first exaflop machine to be entirely built with domestic technology, including, of course, the microprocessors.

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China Preps Godson Chip for Supercomputing Duty

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